The present invention relates to a multiphase waveform generator, and more particularly, to a multiphase waveform generator capable of performing phase calibration and phase calibration method thereof.
The write control waveform for optical disc drives is originated from a bit sequence to be recoded onto the optical disc. Whereas different optical storage medium or data pattern usually derives to different write strategies, in which the recorder laser power is strategically shaped by shifting the falling edges of the waveform of the bit sequence so as to adjust the write time duration in order to achieve proper read characteristics. Thus a multiphase waveform generator is required to support this edge shifting capability.
FIG. 1 is a functional block diagram shows a multiphase waveform generator of the related art. A multiphase waveform generator 100 receives an input signal SIN and a delay parameter n, shifts edges of the input signal SIN by a delay time DTn according to the delay parameter n to generate a phase-modified signal SOUT. The edges of the input signals SIN to be shifted can be the falling edges. On the other hand, the multiphase waveform generator 100 can also be used to shift the rising edges of the input signal SIN. In practical, the delay parameter n could be time-variant or time-invariant. Typically, the delay parameter n is an integer from 0 to a preset number N, which means to let the delay time DTn=n*ΔT with ΔT=T/N and T being the bit time interval. FIG. 2 shows an example. Suppose the bit sequence is 1101 in which the falling edge of the input signal SIN is positioned at t1. The edge shift according to a delay parameter n=2 shows a delay time DTn=2*ΔT such that the falling edge of the phase-modified signal SOUT is positioned at t1+2*ΔT.
Please refer back to FIG. 1. The multiphase waveform generator 100 comprises a delay module 110 and a selection module 130. The delay module 110 comprises M serially connected delay units 115 which delay the input signal SIN and generate M+1 delayed signals, denoted by D0, D1, D2 . . . , DM. Typically, M is a number much larger than N for a practical application. Note that, the delayed signal D0 with zero delay time is just the input signal SIN. The selection module 130 comprises a control signal generator 135 and a multiplexer 140. The multiplexer 140 selects one of the M+1 delayed signals (D0, D1, D2 . . . , DM) according to a control signal CTRL to form the phase-modified signal SOUT. The possible states of the control signal CTRL are denoted by CTRL0, CTRL1, CTRL2, . . . , CTRLM, which instructs the multiplexer 140 to select the delayed signal D0, D1, D2 . . . Dm, respectively. The control signal generator 135 receives the delay parameter n and generates the control signal CTRL accordingly. As is well known in the art, the phase-modified signal SOUT can be formed by properly toggling the state of the control signal CTRL between CTRL0 and CTRLK with K being a function of the delay parameter n. By this way, the delay time DTn will equal to the delay amount introduced by the first K delay units 115 in the delay module 110. Typically, the relationship between the K and the delay parameter n is stored in a lookup table TnK. Conventionally, the lookup table TnK is identical for each integrated circuit.
Nevertheless, the actual delay amount of the delay units 115 may have some fluctuation due to various conditions, such as fabrication process or temperature. Using identical lookup table TnK may result in that the practical amount of the edge shift, i.e. the DTn, deviates from the expected one, i.e. n*T.